In a server or a personal computer, large capacity semiconductor memories, such as dynamic RAMs, are used in larger quantities. In a system employing these memories in larger quantities, it is a frequent practice that a plurality of memory chips is mounted once on a memory module, which memory module is then plugged into a module socket provided in the system. The purpose of doing so is to assure facilitated memory extension and exchanges. The demand from the market for higher operating speeds and larger capacities is rather strong with these memory modules.
To increase the operating speed of the memory module, the memory module that uses a synchronous memory to speed up data transfer between the memory and the information processor, such as CPU, has come to be used. With the synchronous memory, a memory controller that controls the synchronous memory is provided on the information processor side. The memory controller transmits read or write commands to the synchronous memory in synchronization with a clock from the memory controller so that data may be read out from or written in the memory based on these commands. The inner part of the synchronous memory is pipelined so that the commands sequentially supplied from the memory controller are executed in parallel. In connection with the memory module, employing the synchronous memory, such a system has made its debut in which a terminal resistance is enclosed within a semiconductor memory chip and in which the terminal resistance is controlled to be turned on or off to reduce signal reflections to speed up the data transfer. For example, in DDR2-SDRAM (Double Data Rate 2-Synchronous DRAM) or DDR3-SDRAM (Double Data Rate 3-Synchronous DRAM), a terminal resistance is enclosed at a DQ (data input/output) terminal or a DQS (data strobe) terminal. In addition, a terminal resistance control terminal (On-Die Termination terminal, acronymed to ODT terminal) is provided to control the on/off of the enclosed terminal resistance from outside. With the use of the ODT terminal, the terminal resistance may be controlled from the memory controller to increase the transfer rate.
On the other hand, to enlarge the capacity of the memory module, development of a multi-rank memory module that loads a plurality of memory chips of a plurality of ranks in a single memory module is progressing. The rank is a unit of the memory chips to which a command may be afforded independently from the memory controller side. In the case of a memory module that connects to a data bus of 72 bits composed of 64 data bits and 8 ECC bits, 72/4=18 memory chips are needed in order to have access simultaneously to the 72-bit data, if the memory chip is of a 4-bit formulation. These 18 memory chips are loaded in a 1-rank memory module, whereas a doubled number of memory chips, that is, 36 memory chips, are loaded in a 2-rank memory module. The memory controller affords rank-based write and read commands, no matter whether the memory module is of a single-rank formulation or a multiple-rank formulation. If the memory controller side affords a command as it specifies the rank, the memory chip of the rank, the command is to be afforded to, is selected by a chip select signal from the memory chips of a plurality of ranks, and the command is afforded to the so selected memory chips of the rank of interest.
The semiconductor memory, having enclosed therein the terminal resistance, or the memory module or system, employing the semiconductor memory, having enclosed therein a terminal resistance, is disclosed in Patent Documents 1 and 2. The method for connecting the memory module in a memory system that is able to cope with larger capacities or higher operating speeds is disclosed in Patent Documents 3 and 4.
A memory system, employing a 2-rank memory module, in which the values of the enclosed terminal resistance are dynamically switched, is disclosed in Patent Document 5.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2006-129423A    [Patent Document 2] JP Patent Kokai Publication No. JP-P2008-46797A    [Patent Document 3] JP Patent Kokai Publication No. JP-P2005-346625A    [Patent Document 4] JP Patent Kokai Publication No. JP-P2007-164787A    [Patent Document 5] U.S. Pat. No. 7,342,411